The invention relates to an arrangement for generating a clock signal from a received biphase-modulated signal, comprising a controllable clock signal source, a decision arrangement for sampling the polarity of the received biphase signal at a first sampling instant and at a second sampling instant in a symbol interval, the sampling instants having a fixed time spacing, a first comparator for comparing the polarity samples at the first and at the second sampling instants in the symbol interval with each other, a phase detector having an output for supplying, in response to the output signal of the first comparator, a control signal for controlling the frequency and phase of the clock signal source, and a second comparator for comparing the polarity samples at the same relative sampling instants in two successive symbol intervals with each other.
Such arrangements may find their application in receiving devices for digital signals which are used, for example, in subscriber sets of digital telephone systems.
Such an arrangement is known from Dutch Patent Application 8 401 310 to, which U.S. Pat. No. 4,709,378 corresponds. The two sampling instants, for example, instants tB and tF, are derived from the local controllable clock signal source and are to be synchronized with the received biphase-modulated signal.
The sampling instants are a fixed time interval apart. In said arrangement they are approximately one-third to one-fourth symbol interval apart. There is mention of a state of synchronization when the second sampling instant tF occurs just in the middle of the symbol interval where the biphase signal has a zero crossing. The symbol values at the first instant tB represent the transferred information. To reach this condition of correct synchronization, the sampling instants are shifted relative to the received biphase signal until the sampling instant tF occurs just in the middle of a symbol interval. This shift is realized by applying the generated control signal to the controllable clock signal source which comprises a voltage-controlled oscillator frequency (VCO). The oscillator is slightly reduced or increased depending on the control signal.
It is also possible to have a state of so-called "false" synchronization, which occurs on the boundary between two successive symbol intervals. This state is detected by a 64-counter connected to the output of the second comparator. If the same signal value is detected 64 times in a row, the output of the 64-counter produces a signal to indicate the state of false synchronization.
Said method is data-dependent, however, because if the received signal has the same symbol value for more than 64 symbol intervals in a row, an indication signal of false synchronization is produced erroneously. Such a counter further takes up space.